Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

Abstract Inspired by the challenge of scaling-up existing silicon quantum hardware, we propose a 2d spin-qubit architecture with low compilation overhead. The is based on nanowire split-gate transistors which form 1d chains spin-qubits and allow execution two-qubit operations among neighbors. We introduce junction can couple four nanowires into arrangements via spin shuttling Swap operations. then modular sparse unit cells diagonally-oriented squares along edges junctions corners. Targeting noisy intermediate-scale (NISQ) demonstrators, show that proposed allows for strategies outperform methods chains, exhibits favorable scaling properties enable trading-off overhead colocation control electronics within each square adjusting length. An appealing feature its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes.